1. Technical Field
The present invention relates to semiconductor integrated devices and, in particular, but in non-limiting manner, to an integrated device employing an emitter-switching configuration.
2. Prior Art
One particular type of device in an emitter-switching configuration is constituted by a bipolar transistor and an electronic switch in series with the emitter of the bipolar transistor. The opening of the electronic switch enables the bipolar transistor to be turned off extremely quickly and this configuration is therefore commonly used in applications in which the bipolar transistor is required to be able to switch quickly between its conduction and turned-off states.
Typically, the bipolar transistor is a high-voltage power transistor and the electronic switch is constituted by a low-voltage bipolar power transistor in which the emitter terminal of the high-voltage transistor is connected to the collector terminal of the low-voltage transistor; the high-voltage transistor typically has a collector-base junction breakdown voltage with open emitter (Bv.sub.cbo) which may reach 1000V, whereas the low-voltage transistor has a breakdown voltage of between 20V and 50V.
In a device in an emitter-switching configuration integrated in a chip of semiconductor material in which the substrate of the chip is part of the collector region of the high-voltage transistor, the low-voltage transistor can be formed inside the emitter region of the high-voltage transistor.
By way of example, a prior art integrated structure formed with the use of the VIPower process (VIPower is a trade mark of SGS-THOMSON MICROELECTRONICS S.r.l.) will be considered. In the VIPower process, the chip of semiconductor material is constituted by a semiconductor substrate with a first type of conductivity, on which an epitaxial layer doped with the same type of impurities is formed. High-voltage transistors are constructed with a structure with completely vertical conduction in which the various P-N junctions are buried in the epitaxial layer and the collector electrode is formed on the back of the chip, that is, on the opposite face of the substrate to that with the epitaxial layer. This construction process is described in European patent application EP-322040 in the name of SGS-THOMSON MICROELECTRONICS S.r.l.
A schematic, perspective view of a portion of this integrated device is shown in FIG. 1a. The integrated device is formed in a chip 100 of semiconductor material comprising a substrate 105 of monocrystalline silicon strongly doped with N-type impurities (N+); a first epitaxial layer 110 with the same type of conductivity N but with a low concentration of impurities (N-) is formed on the substrate 105 by epitaxial growth.
P-type regions having a concentration of impurities of intermediate value (P) are formed by implantation on the surface of the epitaxial layer 110; regions with N-type doping are then formed on these P-type regions by a subsequent implantation step. A second N-type epitaxial layer 115 having a (greater concentration of impurities than that of the first layer 110 is formed thereon by epitaxial growth.
During this stage, which takes place at high temperature, the implanted P-type and N-type regions described above extend by diffusion in the two epitaxial layers, giving rise to buried regions which define buried P-N junctions. In particular, the P-type region 120 constitutes a buried base region of the high-voltage transistor, whereas the N-type region 125 forms a buried region constituting the emitter region of the high-voltage transistor and the collector region of the low-voltage transistor.
A P-type region 130 having a high concentration of impurities is then formed in the second epitaxial layer 115 by known masking and diffusion techniques; this region 130 extends all the way through the second epitaxial layer 115 and is connected to the buried base region 120 of the high-voltage transistor, constituting a deep base contact region of that transistor.
An N-type region 135 with a high concentration of impurities is then formed by similar implantation techniques (or alternatively by a deposition process) and diffusion techniques and extends in the second epitaxial layer 115 as far as the respective buried region 125.
A P-type region 140 which defines the base region of the low-voltage transistor and a further high-concentration N-type region 145 which defines the emitter region of the low-voltage transistor are then implanted and diffused by similar techniques.
Openings for contact with surface regions of the various components are then formed on the front face of the chip which is covered by an insulating layer 150 (typically silicon dioxide) by known deposition, masking and etching techniques. In particular, the hole 155 defines a region for contact with the base region 120, 130 of the high-voltage transistor and the openings 160 and 165 define a region for contact with the base region 140 and a region for contact with the emitter region 145 of the low-voltage transistor, respectively.
Metal strips formed by a subsequent metallization step are in contact with surface regions of the various components in the respective openings defined above. In particular, the metal strip 170 in contact with the base region 120, 130 of the high-voltage transistor through the hole 155 defines the base electrode (Bh) thereof; the metal strips 175 and 180 in contact with the base region 140 and the emitter region 145, respectively, of the low-voltage transistor through the openings 160 and 165 define the base electrode (Bl) and the emitter electrode (El) of the low-voltage transistor Tl, respectively.
A metal layer 185 formed on the base of the chip, that is, on the free surface of the substrate 105, constitutes the collector electrode (Ch) of the high-voltage transistor.
In plan, the structure described above has so-called interdigitated geometry in which the emitter electrode of the low-voltage transistor is spread out in the form of a comb with elongate portions (fingers) within the base electrode of the high-voltage transistor. Each individual elongate portion of the emitter electrode of the low-voltage transistor disposed between two adjacent fingers of the base electrode of the high-voltage transistor is constituted by a pair of fingers between which there is a metal strip; this set of metal strips constitutes the base electrode of the low-voltage transistor.
This structure is clearly visible in FIG. 1b, which is a plan view of the entire device before the metallization step. The darkened regions represent the contact openings cut in the insulating layer 150; in particular, the finger-like structure of the hole 155 for contact with the base of the high-voltage transistor and the finger-like structure of the hole 165 for contact with the emitter of the low-voltage transistor, within which there are openings 160 for contact with the base of the same low-voltage transistor, can be seen.
In the interdigitated structure described above, the emitter regions of the two power transistors have long perimeters and their emitter-base junctions therefore have low resistance enabling the power transistors to withstand the application of large currents.
This known integrated circuit has some disadvantages. Experimental analysis has shown that, in applications in which the power device described above is subject to large switching currents applied between the collector terminal Ch of the high-voltage transistor and the emitter terminal El of the low-voltage transistor, and to very rapid variations of the potential of the collector terminal of the high-voltage transistor over time (dV/dt), an extension of the turn-off times occurs. This problem limits the frequency response of the device since it cannot be used in applications in which it is made to switch rapidly between its conduction and turned-off states.